1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an internal constant voltage control circuit for a semiconductor memory device capable of being stably operated at a lower temperature.
2. Description of the Prior Art
As shown in FIG. 1, an internal constant voltage control circuit for a semiconductor memory device according to a conventional art includes: a current source 110 for receiving a supply voltage Vcc when switches S1, S2 are turned on and outputting current I.sub.R ; a voltage output unit 120 for generating voltage V.sub.LB in accordance with the output current I.sub.R of the current source 110; a level shifter 130 for determining voltage V.sub.LN in accordance with supply voltage Vcc being applied thereto; and a buffer 140 for differentially amplifying the output voltage V.sub.LB of the voltage output unit 120 and the output voltage V.sub.LN of the level shifter 130 and generating internal voltage V.sub.L.
In the current source 110, there is formed a current mirror which includes a PMOS transistor M1 to the source of which is applied supply voltage Vcc, and another PMOS transistor M2 which receives supply voltage Vcc via a variable resistance R.sub.R. The gate and drain of the PMOS transistor M1 and the gate of the PMOS transistor M2 are connected in common to a node which is earthed sequentially via an NMOS transistor M3 and the switch S1. The drain of the PMOS transistor M2 is grounded sequentially via the NMOS transistor M4 and the switch S2 and at the same time it is connected to the respective gates of the NMOS transistors M3, M4. The connection node between the gates of the NMOS transistors M3, M4 is applied to the gate of the NMOS transistor M5 of the voltage output unit 120. Here, to the variable terminal of the variable resistance R.sub.R there is applied a supply voltage Vcc.
Also, in the voltage output unit 120, the drain of the NMOS transistor M5 is connected to the variable resistance R.sub.L through which is applied the supply voltage Vcc. The source of the NMOS transistor M5 is connected to ground voltage via a switch S3. The variable terminal of the variable resistance R.sub.L is connected to the level shifter 130 via a switch S4. A connection node between the variable resistance R.sub.L and the NMOS transistor M5 is connected to the level shifter 130 via a switch S5.
In the level shifter 130, a condenser (or capacitor) C1 having applied thereto the supply voltage Vcc and the switch S4 in the voltage output unit 120 are respectively connected to the gate of a PMOS transistor M6 (to the drain of which is applied supply voltage Vcc). The PMOS transistor M6 is connected to ground voltage via diodes M7, M8 wherein the gate and the drain of each of the diodes M7, M8 are connected to each other, so that voltage V.sub.LB is outputted from a connection node between the PMOS transistor M6 and the diode M7.
Referring to the buffer 140, the gate and drain of a PMOS transistor M9 applied thereto by supply voltage Vcc and the drain of a PMOS transistor M10 are connected in common to a node which is connected to the drain of an NMOS transistor M11 (to the gate of which is applied the output voltage V.sub.LB of the voltage output 120). The drain of the NMOS transistor M11 is connected to the drain of an NMOS transistor M12 (to the gate of which is applied the output voltage V.sub.LN of the level shifter 130). The drain of the PMOS transistor M10 is connected to the drain and the gate of the NMOS transistor M13, respectively, so that an internal voltage V.sub.L can be generated from the connection node. The sources of the NMOS transistors M11, M12, M13 are connected to ground voltage via an NMOS transistor M14 (to the gate of which is applied a bias voltage V.sub.B). Here, reference numeral C2 denotes a condenser connected between the gate of the NMOS transistor M11 and supply voltage Vcc, and reference numeral C3 denotes a condenser connected between the gate of the NMOS transistor M12 and ground voltage.
The operation of the thusly constituted conventional voltage control circuit for a memory device will now be described.
First, with power turned on, when a control signal .O slashed.1 is turned on, the current I.sub.R flows through the current source 110. The current I.sub.R flows to the PMOS transistor M2 in accordance with the PMOS transistors M1, M2, M3 serving as a current mirror. A gate voltage for the NMOS transistors M3, M4 is determined in accordance with the current I.sub.R. At this time, the gate voltage of the NMOS transistor M4 in the current source 110 becomes equivalent to a gate voltage of the NMOS transistor M5 of the voltage output unit 120.
Therefore, in accordance with the gate voltage of the NMOS transistor M6 the current I.sub.L flows through the voltage output unit 120, so that the supply voltage Vcc serves to generate the voltage V.sub.LB which is pressure-reduced to a predetermined extent in the variable resistance R.sub.L, and the pressure-reduced voltage V.sub.LB is also applied to a connection node N.sub.B of the variable terminal of the variable resistance R.sub.L.
When a control signal .O slashed.2 is turned on, the switches S4, S5 are turned on to thereby transmit the voltage in the variable terminal of the resistance R.sub.L to the level shifter 130, and in accordance with the resistance R.sub.L the voltage which is pressure-reduced to a predetermined extent is transmitted to the buffer 140.
At this time, the voltage V.sub.LN in the level shifter 130 is determined in accordance with the PMOS transistors M6, M7, M8. The gate voltages V.sub.GS of the transistors M7, M8 are determined in accordance with a gate voltage V.sub.GS6 of the PMOS transistor M6, so that because the gate voltage V.sub.GS6 of the PMOS transistor M6 denotes `V.sub.DS6 `, the value of the voltage V.sub.LN becomes `2V.sub.GS `.
The gate voltage V.sub.GS6 of the PMOS transistor M6 is determined by the current I.sub.L flowing through the variable resistance R.sub.L, wherein the current I.sub.L is controlled by the gate voltage of the NMOS transistor M5.
In the buffer 140, when the bias voltage V.sub.B is turned to a high level and the NMOS transistor M14 is turned on, the NMOS transistors M11, M12 respectively serving as a differential amplifier differentially amplifies the output voltage V.sub.LB of the voltage output unit 120 and the output voltage V.sub.LN if the level shifter 130. In accordance with the obtained difference the current flowing through the PMOS transistor M10 is determined for thereby generating the internal voltage V.sub.L.
The level of the internal voltage V.sub.L is rendered to follow the higher level of the input voltages V.sub.LN, V.sub.LB.
That is, with power turned on, during a time in which supply voltage Vcc is being turned to `5 V`, the output voltage V.sub.LN of the level shifter 130 is larger than the output voltage V.sub.LB of the voltage output unit 120, thereby starting the operation of the NMOS transistor M12. From a time point in which the supply voltage Vcc is becoming larger than `5 V`, the voltage V.sub.LB becomes larger than the voltage V.sub.LN, so that with the NMOS transistor M11 starting its operation, the internal voltage V.sub.L is generated in accordance with a graph as shown in FIG. 2, whereby `3.3 V` of constant voltage is generated around the operative voltage (5 V) with regard to the external voltage Vcc.
According to the above-described operation, the internal voltage V.sub.L is generated in accordance with the current I.sub.R which is generated by a difference between a high threshold voltage of the PMOS transistor M2 and a standard threshold voltage of the PMOS transistor M1, thereby maintaining a constant voltage irrespective of a temperature variation.
However, the conventional voltage control circuit generates a constant voltage with regard to a temperature variation, whereby a larger current is flowed therethrough during a low temperature operation than during a high temperature operation. Also, the conventional voltage control circuit causes a signal transition time to be faster for thereby decreasing a timing margin, and because a large amount of current being flowed therethrough leads to noise around a power source wire and a signal wire, there may occur an error operation.
That is, as shown in FIG. 2, when around supply voltage Vcc (=5 V) the NMOS transistors M11, M12 are respectively turned on, the current flow becomes increased, whereby the level of the internal voltage V.sub.L is raised to as high as the voltage difference .DELTA.V.sub.L for thereby resulting in an error operation.